| AMD-K6 | Intel Pentium Pro |
| x86 Decoders | 2 Sophisticate, 1 long, 1 vector | 1 Sophisticated, 2 simple |
| Decode Bandwidth: 32-bit typ/max | 1.9/2.0 | 2.1/3.0* |
| Decode Bandwidth: 16-bit typ/max | 1.8/2.0 | 1.5/3.0* |
| Average RISCops/x86: 32-bit code | 1.2 (lower is better) | 1.5* |
| Average RISCops/x86: 16-bit code | 1.5 (lower is better) | 2.0* |
| Maximum ROp Issue Rate | 6 | 5 |
| Speculative Execution | Yes | Yes |
| Out of Order Execution | Yes | Yes |
| Physical Registers | 48 | 40 |
| Centralized Buffer max/active | 24/18 | 40/20 |
| FPU Multiply/ADD Latency | 2/2 | 5/3 |
| Pipeline Stages | 6 | 12 |
| Misaligned Loads | 1 cycle penalty | 6 cycle penalty |
| Branch History Table | 8192 entries | 512 entries |
| Branch Prediction Accuracy | 95% | 85-90% |
| Misprediction Penalty | 1-4 (Short Pipeline) | 10-15 cycles |
| Instruction/Data TLB | 64/128 entries | 32/64 entries |
| L1 Instruction-Cache | 32KB +Predecode
2-Way Set-Assoc. | 8KB
2-Way Set-Assoc. |
| L1 Data Cache | 32KB, 2-Way Set-Assoc.
(Load+Store)/cycle | 8KB, 4-Way Set-Assoc.
(Load+Store)/cycle |
| Local Bus Bandwidth | 528 MB/sec | 528 MB/sec |
| Local Bus Latency | 2 clocks | 5-7 clocks |
| * "Nx686 Goes Toe-to-Toe with Pentium Pro", Microprocessor Report, Vol.9 No.14, Oct. 23, 1995, MicroDesign Resources |
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